Although the POCSAG code is becoming widely known, in order to understand the present invention it is worth mentioning the signal and code word formats of POCSAG and in this respect reference is made to FIGS. 1 and 2 of the accompanying drawings. FIG. 1 shows the signal format which comprises a preamble 10 of at least 576 bits, comprising alternate ones and zeroes, and a series of batches 12, 14, each of 544 bits. The preamble 10 at its shortest duration has a number of bits corresponding to one of the batches plus a 32-bit code word. A batch 12 or 14 comprises a 32-bit synchronisation code word 16 and eight frames 18, each frame comprising two code words 20, each 32 bits in length. Thus each batch 12, 14 is formed by seventeen code words 20, each 32 bits long.
As described above, the POCSAG format is representative of one in which a batch consists of n words; a word consists of m bits; and the preamble has a length equal to at least n+1 words; that is, the preamble is at least m (n+1) bits. Thus in the POCSAG format n=17, m=32, and the preamble is at least 32 (17+1)=576 bits long.
There are two types of code words 20: address code words 22 and message code words 24. The first bit of a code word determines whether it is an address code word or a message code word, depending on whether its value is zero or one. In the case of an address code word, bits 2 to 19 are address bits corresponding to the eighteen most significant bits of a 21-bit identity code assigned to the paging receiver. The three least significant bits are not transmitted but serve to define the frame within a batch in which the address code word must be transmitted. Four discrete addresses are assigned to each paging receiver having a given 21-bit identity code, selection of a particular one of the four addresses depending on the values assigned to the bits 20 and 21. Bits 22 to 31 are cyclic redundancy check bits and the final bit, bit 32, is chosen to give even parity on the complete code word.
In the case of a message code word 24, the bits 2 to 21 are assigned as message bits which do not follow the allocations of the address code word 22, whereas bits 22 to 32 do.
A batch is formed by a synchronisation code word which precedes in time sixteen other code words. Since the identity of a paging receiver is defined by an address code word 22 transmitted in a given time frame 18 within a batch 12, 14, it is unnecessary for the paging receiver to receive any address code words other than those in its allocated frame. Thus the paging receiver may switch off when other frames are being transmitted, thus providing a battery saving capability. In any transmission of a batch, an idle (unallocated) address code word is transmitted in the event that a particular code word location within that batch is not required for the transmission of a paging call.
A paging call requiring transmission of message code words 24 is formatted such that an appropriate number of message code words 24, related to the length of the message, are concatenated onto one of the address code words 22 assigned to the particular paging receiver. Although message code words 24 (FIG. 2) may continue into a subsequent batch due to the length of the messages, the normal batch structure, that is, sixteen code words 20 preceded by a synchronisation code word 16, is maintained.
With the POCSAG signalling structure, a paging decoder has to synchronize itself first with the preamble 10 and second with the synchronisation code word 16. Unless the paging decoder is synchronised to the synchronisation code word, it will be unable to decode successfully address code words in their assigned frame.
In operation, a paging receiver inits carrier-off mode, i.e. when there are no transmissions from its base station, is usually switched on once every seventeen code words for a duration equal to that of a 32-bit code word in order to detect the preamble bit pattern which may be transmitted. Since the preamble for POCSAG is at least eighteen code words long it will quickly be detected. Thereafter the paging receiver is continuously energised for a duration of eighteen code words in order to detect the synchronisation code word 16 which is concatenated onto the preamble 10. Then the paging receiver assumes its data receive mode and switches its receiver section off until its assigned time frame and then switches it on for that time frame in order to decoder address code words. Then the decoder will be switched off until the time slot allocated to the synchronisation code word in a subsequent concatenated batch, at which time the decoder is switched on in order to decode that synchronisation code word and subsequently the address code word in the following allocated frame. If the synchronisation code word is not detected, then the paging decoder may not decode address code words in the allocated subsequent time frame. Thus it is essential to achieve and maintain word synchronisation. It is important that synchronisation and address code words be decoded acceptably in order to keep a sufficiently low falsing rate.
British Patent Specification No. 2,086,106A discloses a pager decoding circuit with an intelligent synchronisation circuit. This known circuit employs a synchronisation strategy which tolerates at least some degree of error in an attempt to achieve batch synchronisation. The decoding circuit includes means for examining the received bit pattern in order to search initially for the presence of the preamble. When a match or near match to the preamble bit pattern is detected, the decoding circuit examines the received bit pattern for the synchronisation code word. When a match or a near match to the synchronisation code word is achieved, the decoding circuit is deemed to be in batch synchronisation, in which case it is then able to examine the address code words in the assigned frame in order to detect the receipt of a paging call.
The decoding circuit then examines each synchronisation time slot in subsequent batches in order to detect the synchronisation code word in those batches and thereafter detect address code words in the allocated time frame within those batches. If neither a match between the received bit pattern and the stored reference synchronisation code word is achieved nor a near match to a certain number of bits in error is obtained, then the address frame is not examined for address code words. If the synchronisation code word is again not detected in the time slot allocated for the synchronisation code word in the next batch, assuming that a next batch has been transmitted, then the decoding circuit deems that batch synchronisation has been lost and then reverts to its carrier-off mode, in which it examines the received bit pattern for the preamble bit pattern or a near match to it.
When examining the received bit pattern for the presence of the preamble, the known circuit switches on for one code word slot in each batch, as before, thus guaranteeing detection of the preamble if it is being transmitted. Once the preamble has been detected, the receiver examines the bit pattern for the synchronisation code word. When this has been detected, the known circuit assumes a data receive mode as described previously.
This known decoding circuit has two drawbacks. First, it cannot resume correct batch synchronisation if a long fade, i.e. greater than eighteen code words (worst case), occurs, causing irrecoverable errors in the received bit pattern because the circuit will have reverted to preamble detection operation in a carrier-off mode while coded data is still being transmitted. Consequently the probability of detecting the preamble in the coded data is very low, causing batches of data (e.g. addresses) to be overlooked. The second drawback in the operation of this known decoding circuit may occur if the paging receiver is used in a heavily loaded, zoned transmission system. A zoned transmission system as specified within the POCSAG description would allow for the transmission of a preamble immediately concatenated to the end of a batch of code words if the paging receiver were in an overlap region of two transmission zones and the data transmission period in the first zone were continuous for the complete zone time period. Under such circumstances the known circuit would not detect the transmitted preamble (assuming that the received bit pattern is decodable as preamble) since immediately following failure to detect a synchronisation code word, as would occur at the end of transmission on one zone or in an unzoned system, the known decoder will be examining only the received bit pattern for the following synchronisation code word, which will not be present because preamble is being transmitted.